This application relates to semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry.
Dynamic random access memory (DRAM) circuitry is typically formed by forming a number of different layers of material over a substrate such as a silicon wafer, and then etching such layers into desired substrate features such as conductive word lines, capacitor containers, capacitor structures, and bit lines to name just a few. Efforts continue to be made to reduce the number of processing steps and processing complexity thereof.
This invention arose out of concerns associated with improving the methods through which dynamic random access memory (DRAM) circuitry is formed. This invention also arose out of concerns associated with reducing processing complexities associated with the fabrication of DRAM circuitry.
Methods of forming dynamic random access memories (DRAM) are described. In one embodiment, an insulative layer is formed over a substrate having a plurality of conductive lines which extend within a memory array area and a peripheral area outward of the memory array. Capacitor container openings and contact openings are contemporaneously etched over the memory array and conductive line portions within the peripheral area respectively.
In another embodiment, a patterned masking layer is formed over a substrate having a plurality of openings formed within an insulative layer, wherein some of the openings comprise capacitor container openings within a memory array and other of the openings comprise conductive line contact openings disposed over conductive lines within a peripheral area outward of the memory array. With a common patterned masking layer, unmasked portions of a capacitor electrode layer are removed within the memory array and material from over portions of the conductive lines within the peripheral area is removed sufficient to expose conductive material of the conductive line portions.
In yet another embodiment, a common etch chemistry is used to remove selected material of an insulative material layer formed over conductive lines within a peripheral area and material of a storage capacitor electrode layer.
In yet another embodiment, a plurality of conductive plugs are formed over substrate node locations over which storage capacitors are to be formed. After forming the plugs, insulative material over conductive lines within a peripheral area is removed to first expose conductive material of the conductive lines.